By Philipp Grabher, Johann Großschädl, Simon Hoerder, Kimmo Järvinen, Dan Page (auth.), Bart Preneel, Tsuyoshi Takagi (eds.)
This ebook constitutes the court cases of the thirteenth overseas Workshop on Cryptographic and Embedded platforms, CHES 2011, held in Nara, Japan, from September 28 until eventually October 1, 2011.
The 32 papers awarded including 1 invited speak have been conscientiously reviewed and chosen from 119 submissions. The papers are equipped in topical sections named: FPGA implementation; AES; elliptic curve cryptosystems; lattices; aspect channel assaults; fault assaults; light-weight symmetric algorithms, PUFs; public-key cryptosystems; and hash functions.
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Additional info for Cryptographic Hardware and Embedded Systems – CHES 2011: 13th International Workshop, Nara, Japan, September 28 – October 1, 2011. Proceedings
FPGA vendor agnostic true random number generator. In: Field Programmable Logic and Applications (FPL), pp. 1–6 (2006) 13. : Physical unclonable functions for device authentication and secret key generation. In: Design Automation Conference (DAC), p. 914 (2007) 14. : True Random Number Generators for Cryptography. In: Cryptographic Engineering. Springer, Heidelberg (2009) 15. : A provably secure true random number generator with built-in tolerance to active attacks. IEEE Transactions on Computers 58, 109–119 (2007) 16.
Before moving onto the TRNG system performance evaluation, we shall first discuss the results of our investigation on the maximum achievable resolution of the PDLs. We set up a highly accurate delay measurement system similar to the delay characterization systems presented in [9,7,6]. The circuit under test consists of four PDLs each implemented by a single 6-input LUT. The delay measurement circuit as shown in Figure 9 consists of three flip-flops: launch, sample, and capture flip-flops. At each rising edge of the clock, the launch flipflop successively sends a low-to-high and high-to-low signal through the PDLs.
LNCS, vol. 1673, pp. 291–300. Springer, Heidelberg (1999) 13. : Improving program eﬃciency by packing instructions into registers. In: ISCA, pp. 260–271 (2005) 14. : Interfacing a high speed crypto accelerator to an embedded CPU. In: Asilomar Conference on Signals, Systems, and Computers, vol. 1, pp. 488–492 (2004) 15. : An evaluation of hash functions on a power analysis resistant processor architecture. In: Ardagna, C. ) WISTP 2011. LNCS, vol. 6633, pp. 160–174. Springer, Heidelberg (2011) 16.
Cryptographic Hardware and Embedded Systems – CHES 2011: 13th International Workshop, Nara, Japan, September 28 – October 1, 2011. Proceedings by Philipp Grabher, Johann Großschädl, Simon Hoerder, Kimmo Järvinen, Dan Page (auth.), Bart Preneel, Tsuyoshi Takagi (eds.)